The wire bonding is adopted in the conventional packaging technologies and it needs processes including a lead frame or a substrate, die attach, bonding, molding, trim, form, and so on. The packaged integrated circuit (IC) is several times the size of the chip. However, the I/O (input/output) pins are rapidly increased and the developed tendency for electronic devices is toward miniaturization, so the wire bonding can not satisfy the request. The various package technologies, such as Tape Automated Bonding (TAB), Ball Grid Array (BGA), Flip-Chip, etc., are developed in succession for improving or remedying the drawbacks of the conventional package technology.
The aforementioned Flip-Chip technology is an advanced package technology for connecting chip and substrate. During packaging process, the chip is “flipped” and so the pads of the chip connect with the pads of the substrate. The materials of substrate suitable for Flip-Chip generally include ceramic substrate, silicon wafer, polymer, glass and so on. The applications thereof are very wide, including computer, PCMCIA card, martial equipment, personal communications, clocks, watches, LCD, SAW (surface acoustic wave) device, etc.
To employ Flip-Chip mainly has two advantages. First the signal transmitting distance can be reduced and so it is suitable for package of high-speed device; second, the size of the packaged chip can be reduced as the size of chip before packaging, so it is suitable for the IC device requiring a smaller packaging size.
Although the Flip-Chip technology has some advantages, it still has some inherent drawbacks or limitations, e.g.: high precise assembly, curing time, low reliability for certain substrates, etc. For solving and improving these inherent drawbacks or limitations, different Flip-Chip technologies are made to overcome these inherent drawbacks. Some Flip-Chip technology will be described and illustrated below.
In the U.S. Pat. No. 6,310,421 and U.S. Application No. 20030009864, an air gap package technology is disclosed. As shown in FIG. 1A, it shows a packaging structure disclosed in the U.S. Pat. No. 6,310,421. The air gap package technology is to form an air gap 117 on an active region 105 of an electronic device 110 among air gap layers 115 and 116 and then the chip is flipped on a substrate 120. The hermeticity of the structure formed by the air gap package technology is very good, but it needs two developments and so the process thereof is more complicated and, further, the height of the structure is higher.
Film package technology, as disclosed in the U.S. Pat. No. 6,492,194, WO 99/43084 and WO 03/012856, employs a film formed on an electronic device and a substrate and presses the film to tightly rest on the electronic device and the substrate. As shown in FIG. 1B, it is the diagram of the structure disclosed in WO 03/012856, the film 240 rests tightly on the electronic device 210 and the structure 220. However, the hermeticity of the structure is insufficient, especially the portion of the film 270 at the side of the electronic device 210 becomes thick when the film 240 is pressed and formed, as shown in FIG. 1C. Therefore, gas may easily pass through the portion of the film 270. Moreover, the voids near the attaching point between the portion of the film 270 function as dropper to decrease the hermeticity of the structure. Furthermore, due to the moisture, etc. attacking the packaged device during the many times of lowering and raising temperature, the characteristics of device will be changed or the packaged device will be damaged. Hence, another film 260 must be formed on the film 240 to enhance the hermeticity and so the complication of the process is higher.
In the U.S. Pat. No. 6,078,229, it discloses a packaging structure with resin film 330 and the method of making the same, as shown in FIG. 1D. The advantage thereof is that the metal layer does not need to be formed and so weight and cost are reduced. Nevertheless, the resin film 330 must to be formed several openings thereon for not recovering a vibration cavity 317 of a surface acoustic wave device 314 and the bump 316, the process is required higher preciseness and is more complicated.
Another package technology is the Underfill package technology. FIG. 1E shows the structure of Underfill package technology disclosed by the U.S. Pat. No. 5,969,461. The resin 440 will flow into the space between the electronic device 410 and the substrate 420 during the time from injecting the resin 440 to the resin 440 have been cured. Therefore, the dam 480 is added for avoiding the resin 440 attaching the active region of the electronic device 410 and effecting the characteristic of the electronic device, such as surface acoustic wave device. Furthermore, the redundant portion of the resin must be cleaned. Hence, the process is more complicated and increases cost thereof.
In the U.S. Pat. No. 6,262,513, encapsulation resin package technology is disclosed, as shown in FIG. 1F. A resin layer 540 is recovered on an electronic device 510 and the substrate 520. The resin layer 540 must be low fluid for avoiding flowing into the space between the electronic device 510 and the substrate 520 and effecting the characteristic of the electronic device as the Underfill package technology. Nevertheless, the resin layer 540 has the problem of thermal expansion when heating for curing the resin. SiO2 is added into the resin layer 540 in order to reduce a thermal stress due to the difference of thermal expansion coefficient, but it results in decreasing the adhesion between the resin layer 540 and wires 590 and the hermeticity of the structure is so unsatisfactory.